Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs
Pedro M. Figueiredo, João C. VitalOffset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Категорії:
Рік:
2009
Видання:
1
Видавництво:
Springer
Мова:
english
Сторінки:
395
ISBN 10:
1402097158
ISBN 13:
9781402097157
Серії:
Analog Circuits and Signal Processing
Файл:
PDF, 10.06 MB
IPFS:
,
english, 2009
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